High Performance Low Latency 16×16 bit Booth Multiplier using Novel 4-2 Compressor Structure

  • Ali Rahnamaei Department of Electrical Engineering, Ardabil Branch, Islamic Azad University, Ardabil, Iran.
  • Azadeh Kiani Sarkaleh Department of Electrical Engineering, Rasht Branch, Islamic Azad University, Rasht, Iran.
Keywords: Booth Multiplier, Modified Booth Encoding scheme, 4-2 Compressor, Radix-4, Low Latency

Abstract

In this article, the design procedure of a low latency Booth multiplier has been proposed. With the help of a novel 4-2 compressor, a high-performance 16×16 bit Booth multiplier has been implemented, which depicts high operating frequency. To achieve this, the proposed 4-2 compressor has been utilized successively in the Partial Product Reduction Tree (PPRT) of the multiplier and by means of radix-4 Booth scheme, the multiplier has been designed. The Partial Product (PP) generation circuitry is also based on the other work published by the authors which enables the designed structure to work at the frequency of 350MHz. The main advantage of the designed compressor is the elimination of the middle stage inverters between cascaded blocks of PPRT which considerably enhances the speed of whole system. Simulation results for TSMC 0.18µm CMOS technology and 1.8V power supply have been demonstrated to confirm the correct operation of proposed 4-2 compressor. According to the results, the achieved delay of the critical path for hard test and high capacitive load, equal to 100fF, is 936ps while a power consumption of 255.15µW has been achieved at the operating frequency of 100MHZ.

References

[1] AC Davies, and YT Fung, “Interfacing a hardware multiplier to a general-purpose microprocessor,” Microprocessors, Volume 1, Issue 7, Pages 425-432, October 1977.
[2] Andrew D. Booth, “A signed binary multiplication technique,” The Quarterly Journal of Mechanics and Applied Mathematics, Volume IV, Pt. 2, 1951.
[3] C. S. Wallace, “A suggestion for a fast multiplier,” IEEE Trans. on Computers, vol. 13, pp. 14-17, 1964.
[4] L. Dadda, “Some schemes for parallel multipliers,” Alta Frcquetiza, vol. 34, pp. 349-356, 1965.
[5] Abu-Khater I.S., Bellaouar A. and Elmasry, M.I., “Circuit Techniques for CMOS Low-Power High-Performance Multipliers,” IEEE Journal of Solid-State Circuits, Vol. 31, Issue 10, pp. 1535-1546 , 1996.
[6] Ohkubo N., Suzuki M., Shinbo T. et al., “A 4.4 ns CMOS 54 54-b Multiplier Using Pass-Transistor Multiplexer,” IEEE Journal of Solid-State Circuits, Vol. 30, Issue 3, pp. 251-257, 1995.
[7] Wen-Chang Yeh and Chein-Wei Jen, “High-Speed Booth Encoded Parallel Multiplier Design,” IEEE Transactions on Computers, Vol. 49, No. 7, July 2000.
[8] Hsin-Lei Lin, Chang R.C. and Ming-Tsai Chan, “Design of a Novel Radix-4 Booth Multiplier,” The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, Vol. 2, pp. 837-840, 2004.
[9] Shiann-Rong Kuang, Jiun-Ping Wang, and Cang-Yuan Guo, “Modified Booth Multipliers With a Regular Partial Product Array,” IEEE Transactions on Circuits and Systems—II: Express Briefs, Vol. 56, No. 5, pp. 404-408, May 2009.
[10] A. Fathi, S. Azizian, R. Fathi, H.G. Tamar, “Low latency, glitch-free booth encoder-decoder for high speed multipliers,” IEICE Electronics Express, Vol. 9, No. 16, pp. 1335-1341, 2012.
[11] A. Fathi, S. Azizian, Kh. Hadidi, A. Khoei, “Ultra High Speed Modified Booth Encoding Architecture for High Speed Parallel Accumulations,” IEICE transactions on electronics, Vol. 95, No. 4, pp. 706-709, 2012.
[12] Honglan Jiang, Jie Han, Fei Qiao, and Fabrizio Lombardi, “Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation,” IEEE Transactions on Computers, Vol. 65, No. 8, pp. 2638-2644, Aug 2016.
[13] Liu, Weiqiang, et al, “Design of approximate radix-4 Booth multipliers for error-tolerant computing,” IEEE Transactions on Computers (2017).
[14] D. Radhakrishnan and A. P. Preethy, “Low-power CMOS pass logic 4-2 compressor for high-speed multiplication,” in Proc. 43rd IEEE Midwest Symp. Circuits Syst., vol. 3, 2000, pp. 1296–1298.
[15] Chip-Hong Chang, Jiangmin Gu, and Mingyan Zhang, “Ultra Low-Voltage Low-Power CMOS 4-2 and 5-2 Compressors for Fast Arithmetic Circuits,” IEEE Transactions on Circuits and Systems I, Vol. 51, Issue 10, pp. 1985-1997, 2004.
[16] Amir Fathi, Sarkis Azizian, Khayrollah Hadidi and Abdollah Khoei, “A Novel and Very Fast 4-2 Compressor for High Speed Arithmetic Operations,” IEICE transactions on electronics, Vol. E95-C, No. 4, April 2012.
[17] Amir Fathi, Sarkis Azizian, Khayrollah Hadidi, Abdollah Khoei and Amin Chegeni, “CMOS Implementation of a Fast 4-2 Compressor for Parallel Accumulations,” 2012 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1476-1479, May 2012.
[18] A. Momeni, J. Han, P.Montuschi, and F. Lombardi, “Design and Analysis of Approximate Compressors for Multiplication,” IEEE Transactions on Computers, Vol. 64, No. 4, pp. 984-994, 2015.
[19] Omid Akbari, Mehdi Kamal, Ali Afzali-Kusha, and Massoud Pedram, “Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 25, No. 4, pp. 1352-1361, 2017.
[20] A. Weinberger, “4:2 Carry-Save Adder Module,” IBM Technical Disclosure Bull., Vol. 23, Jan. 1981.
[21] Oklobdzija V.G., Villeger D., and Liu S.S., “A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach,” IEEE Transactions on Computers, Vol. 45, no. 3, pp. 294-306, Mar. 1996.
[22] A. Rahnamaei, G. Zare Fatin, A. Eskandarian, “High speed Radix-4 Booth scheme in CNTFET technology for high performance parallel multipliers,”. International Journal of Nano Dimension, (2019).
[23] R.UMA, Vidya Vijayan, M. Mohanapriya, and Sharon Paul, “Area, Delay and Power Comparison of Adder Topologies,” International Journal of VLSI design & Communication Systems (VLSICS), Vol. 3, No. 1, February 2012.
Published
2020-06-01
How to Cite
Rahnamaei, A., & Kiani Sarkaleh, A. (2020). High Performance Low Latency 16×16 bit Booth Multiplier using Novel 4-2 Compressor Structure. Majlesi Journal of Electrical Engineering, 14(2), 1-9. Retrieved from http://mjee.org/index/index.php/ee/article/view/3293
Section
Articles